The reliability of power interconnect systems in integrated circuits is affected by a phenomenon known as “electromigration”. Electromigration is the flow of metal ions under the influence of high electric current densities. The effects of electromigration in integrated circuits are manifested in the form of voids and hillocks along the power interconnect system in the integrated circuit. These voids and hillocks can result in increased resistance, which leads to large IR drops, can cause degradations in gate delays, and may even be sources of device failure.
Electromigration is becoming even more of a reliability concern as improvements in integrated circuit design are made. As integrated circuits become larger and faster, more current flows through integrated circuits' power interconnect systems. At the same time, lithography and device improvements result in the wire dimensions of the power interconnect system becoming narrower. The combined effect is an increase in current density, which as described above is the force behind electromigration.
To allay reliability concerns associated with electromigration, design of an integrated circuit should include provisions for maintaining current stresses below certain predefined limits. This is typically accomplished by predicting the current density distribution of the power interconnect structure using a modeling tool and comparing the predicted results to electromigration rules. Various electromigration analysis models have been developed to predict current densities of integrated circuit power interconnect systems. Because power interconnect systems are large and complex, however, it is not normally practicable to perform a full analysis at each and every section of the interconnect system. For this reason, existing models typically include approximations and simplifications that render the results inaccurate to some degree.
According to a first electromigration analysis model, known in the art as the “static model,” all transistors of a transistor network coupled to the power interconnect system are assumed to switch simultaneously and all transistors are assumed to draw a certain percentage of their Idsat current when turned on. This percentage is based on the assumption that every transistor is driving a worst case fan out, and will therefore not take into account actual load conditions. In actual networks, however, all transistors do not switch simultaneously. For this reason, the static model overestimates the current flowing through the power interconnect system. Overestimating the current is unfavorable since it results in modifying the power interconnect system design in a way that requires wires of unnecessarily large widths.
Another electromigration analysis model is the “dynamic model”. According to the dynamic model, vector files are employed to more accurately control the switching of the transistors of the transistor network coupled to the power interconnect system. The number of input vectors required is on the order of the number of input signals, which depends on the number of transistors making up the transistor network. Whereas the dynamic model is more accurate than the static model, it is unfavorable since the number of vector files that need to be generated may be prohibitive. Further, if the integrated circuit design is complex, the vector files may be difficult to define or even impossible to generate. Finally, the time to run the model may be so time consuming that the model is of not much practical use.